Verification Plans

Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.

"In this book, Peet gives every engineer trying to do functional verification a jump-start on getting it under control...His technique...is soundly grounded in the real world, honed through years of experience and practice. If you adopt this approach, it will improve the speed with which verification plans are produced, improve their quality, help eliminate redundant work, and reduce unnecessary work...But wait, there's more. Peet not only tells you how to do it, he tells you why you should do it a certain way, and why Hardware Verification Languages give you an advantage (motivation for you to check out the new techniques and ammunition for your presentations to management)...I have been helped already by what Peet gives in his book. I'm keeping my copy right next to Janick's book." (Glenn Hunt, Texas Instruments)